DESCRIPTION
Our Design Verification Engineer will be part of the R&D PLC (Product Life Cycle) and will be responsible for the gates of POC, Unit tests, System tests, and Beta.
Roles & Responsibilities
- Planning the entire system tests, POC tests, and Unit tests.
- Collaboration with the rest of the R&D department such as System Eng. , Physics, Electronics, SW Eng. etc.
- Define and execute an experiment plan both simulative and on the tool for design validation and risk retirement
- Perform advance results analysis and concluding module performance and gaps to address
- Approve final design and specs to be “field ready”.
- A deep part of the position is dealing with the application quality.
- Provide recommendations for performance specs and promote corrective actions for future designs.
- Follow and support module performance and its system impact after its release. (Beta stage)
- Planning Jigs and life span to support the experiment.
Requirements
- B.SC in Electrical Eng, Mechanical Eng. or any related technical degree
- Experience in V&V testing - Big advantage
- Must have experience in PLC (Product Life Cycle)
- Must have experience from a Multidisciplinary companies
- Methodic & Quick learner
- Knowledge in Solidworks, Labview, Matlab, and ArtiosCAD - an advantage
- Excellent interpersonal and leadership skills
- Ability to work and lead complex tasks independently
- Strong written and verbal communication skills, fluent in English
- Working in a Multidisciplinary systems environment - Major advantage